VLSI Design Flow The Y-chart consists of three major domains: - ppt video online download

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The design flow starts from the algorithm, then define the architecture, then mapped onto chip surface i.e., floorplan then define the finite state machines then implement the finite state machine with functional modules, then placing the modules onto the chip surface, then implementing modules with leaf cells (i.e., logic gates) then cell placement and routing then transistor level implementation of leaf cells then mask generation (In standard-cell based design, leaf cells are pre-designed at the transistor level and stored in a library for logic implementation)
VLSI Design Flow The Y-chart consists of three major domains:
behavioral domain, structural domain, geometrical layout domain.
the algorithm, then define the architecture, then mapped onto chip surface i.e., floorplan. then define the finite state machines. then implement the finite state machine with functional modules, then placing the modules onto the chip surface, then implementing modules with leaf cells (i.e., logic gates) then cell placement and routing. then transistor level implementation of leaf cells. then mask generation. (In standard-cell based design, leaf cells are pre-designed at the transistor level and stored in a library for logic implementation)
The use of hierarchy, or divide and conquer technique involves dividing a module into sub- modules and then repeating this operation on the sub-modules until the complexity of the smaller parts becomes manageable.
1. Field Programmable Gate Array (FPGA) 2. Gate Array Design. 3. Standard-Cells Based Design. 4. Full Custom Design.
General architecture of Xilinx FPGAs
XC2000 CLB of the Xilinx FPGA
While the design implementation of the FPGA chip is done with user programming, that of the gate array is done with metal mask design and processing. Gate array implementation requires a two-step manufacturing process: The first phase, which is based on generic (standard) masks, results in an array of uncommitted transistors on each GA chip. These uncommitted chips can be stored for later customization, which is completed by defining the metal interconnects between the transistors of the array.
Basic processing steps required for gate array implementation
Layout views of a conventional GA chip and a gate array with two memory banks
one of the most prevalent full custom design styles which require development of a full custom mask set. The standard cell is also called the polycell. all of the commonly used logic cells are developed, characterized, and stored in a standard cell library. A typical library may contain a few hundred cells including inverters, NAND gates, NOR gates, complex AOI, OAI gates, D-latches, and flip-flops. Each gate type can have multiple implementations to provide adequate driving capability for different fanouts.
The characterization of each cell is done for several different categories. It consists of. delay time vs. load capacitance. circuit simulation model. timing simulation model. fault simulation model. cell data for place-and-route. mask data.
In a strict sense, it is somewhat less than fully custom since the cells are pre-designed for general use and the same cells are utilized in many different chip designs. In a fuller custom design, the entire mask design is done anew without use of any library. In digital CMOS VLSI, full-custom design is rarely used due to the high labor cost. Exceptions to this include the design of high-volume products such as memory chips, high- performance microprocessors and FPGA masters.
For logic chip design, a good compromise can be achieved by using a combination of different design styles on the same chip. The Intel microprocessor chip is a good example of a hybrid full-custom design. Four different design styles on one chip: Memory banks (RAM cache), data-path units consisting of bit-slice cells, control circuitry mainly consisting of standard cells and PLA blocks.